1. Field of the Invention
This invention provides a semiconductor memory in which a normal memory area is divided into a plurality of divided memory areas, a data buffer is provided for each of the divided memory areas, the bit lines of each divided memory area is connected via column selector to a data buffer corresponding to the divided memory area, a buffer changeover switching means are connected between each data buffer and the data bus, a a column accessing is made by turning the buffer changeover switching means in a predetermined sequence while said column selector is controlled by output signals of the column decoder decoding the column address signals.
2. Prior Art
FIG. 2 shows an example of a semiconductor memory. In distinction from the ordinary random access memory (RAM) which may be accessed in random, this semiconductor memory is adapted to write or read signals in a predetermined sequence, and has been evolved as a video signal processing memory.
In the drawing, 1 is a memory area having m pairs of column lines, m being a positive integer. The memory area is divided into p divided memory areas 2.sub.1, 2.sub.2, . . . , 2.sub.p, p being equal to m/n, n being a positive integer smaller than m. Each divided memory area has n pairs of column lines.
3.sub.1, 3.sub.2, . . . , 3.sub.p are column selectors provided in association with the divided memory areas 2.sub.1, 2.sub.2, . . . , 2.sub.p for connecting a bit line pair among n pairs of bit lines of the divided memory areas 2 designated by the output of the column decoder 4. The data buffers 5.sub.1, 5.sub.2, . . . , 5.sub.p are provided in association with the divided memory areas 2.sub.1, 2.sub.2, . . . , 2.sub.p, and connected to the divided memory areas 2.sub.1, 2.sub.2, . . . , 2.sub.p corresponding thereto by way of the column selectors 3.sub.1, 3.sub.2, . . . , 3.sub.p.
Q.sub.b1, Q.sub.b2, . . . , Q.sub.bp are buffer changeover switching transistors connected between the data buffers 5.sub.1, 5.sub.2, . . . , 5.sub.p and the data bus 6, and switched by driving circuits 7.sub.1, 7.sub.2, . . . , 7.sub.p. The driving circuits 7.sub.1, 7.sub.2, . . . , 7.sub.p are connected in tandem and turn on the data buffers 5.sub.1, 5.sub.2, . . . for a certain time at a predetermined sequence. Thus they serve for sequentially connecting data buffers 5.sub.1, 5.sub.2 . . . to data bus 6.
The operation is hereinafter explained. First explaining the reading operation, a pair of the lines of each divided memory area 2 is connected by an output signal of column decoder 4 to a data buffer 5 via column selector 3 and the signal stored in the memory cell is transferred to and stored in data buffer 5. The column address signal is switched and the output signal of the column decoder 4 is switched therewith so that the signal from the next bit line pair is transferred to and stored in data buffer 5. This operation is repeated sequentially until n signals are stored in data buffer 5. The data buffer 5 connected to data bus 6 by one driving circuit 7 outputs n signals sequentially. On termination of signal reading at one divided memory area 2, reading is performed at the next divided memory area 2. In this manner, reading is performed in all of the divided memory areas 2 in a predetermined sequence.
The writing operation is hereinafter explained. Input data signals are input from data bus 6 sequentially. These input data signals are sequentially fetched by one data buffer 5 selected by one driving circuit 7 and, when the number of bits of the signal reaches n, the input data signals are written via column selector 3 into divided memory area 2. After this operation is repeated p times, data are written in the memory cells connecting to all of the bit lines.
The reason the data buffer is not provided for each bit line pair but one data buffer is provided for each of plural pairs of bit lines in the semiconductor memory is to avoid increase in the occupied area.
The above semiconductor memory has one data bus. However, plural data buses may also be provided. FIG. 3 shows the provision of q data buses.
With the above semiconductor memory, reading is performed by forming sequential data by repeating the operation of loading q data of n data signals on the data bus in parallel and performing parallel series conversion n/q number of times.
For writing, input data signals sequentially input are converted into q parallel data, these q parallel data being simultaneously transferred to data buffers 5.sub.1, 5.sub.2, . . . , 5.sub.p. In this case, the drive circuits 7.sub.1, 7.sub.2, . . . , 7.sub.q turn on the buffer switching Q.sub.b1, Q.sub.b2, . . . , Q.sub.bq simultaneously.
After the transfer operations are repeated n/q number of times, and when the n data signals are prepared at the data buffer 5, they are transferred via column selectors 3.sub.1, 3.sub.2, . . . , 3.sub.q to bit line pairs the divided memory areas 2.sub.1, 2.sub.2, . . . , 2.sub.q. This operation is repeated m/n number of times so that data can be written in the selected memory cells connecting to the column lines.
Meanwhile, in a semiconductor memory of the type shown in FIGS. 2 and 3, when there is a trouble in the memory cell by providing a redundant memory area as in the technology described in the Japanese Patent Publication No. 63-29360, it is necessary to increase the substantial production yield by using a redundant memory area in place of the bit in trouble.
However, although the technology of the Japanese Patent Publication No. 63-29360 is effective for the ordinary random access memory RAM, it cannot be applied to a semiconductor memory of the type in which the redundant memory area is divided into plural divided memory areas, data buffers are provided in association with the divided memory areas, column selectors are interposed and accessed in a predetermined sequence by the intermediary of column selectors controlled by a column decoder 4 between the divided memory area and the data buffer by the following reason.
Since the output line of the column decoder 4 is input to plural column selectors 3.sub.1, 3.sub.2, . . . , 3.sub.p in such semiconductor memory, when switching to a redundant memory area as to one bit line in trouble, it is necessary that the signal of the bit line in trouble be not transferred to the data buffer. A method devised to meet such necessity is to inactivate the signal among the output signals of the column decoder 4 which designates the column address including the bit in trouble. However, in such case, the bit line pairs belonging to other divided memory areas are also inactivated as long as they correspond to the same column address so that an ordinary operation cannot be expected. Thus this method cannot be resorted to.
It is also contemplated to make substitution by the redundant memory area with the totality of bit line pairs selected by the output line of the column decoder 4 selecting the bit line in trouble. However, in such case, the area of the redundant memory area is uselessly increased. For this reason, in the semiconductor memory of the type shown in FIGS. 2 and 3, the technology of rescuing the column in trouble by the redundant memory area has not been used.